The invention is concerned with a flash memory device. In particular, the present invention relates to a bitline bias circuit and a NOR flash device including the bitline bias circuit.
Flash memories are basically one type of non-volatile memory, in which data is safely maintained even if its power supply is cut off. Flash memories are used in mobile applications such as digital cameras, cellular phones, PDAs and so forth. This is because the flash memories have low power consumption and free input/output of information. There exist two major types of cell arrays in flash memories: NOR and NAND type cell arrays. A more compact size of memory can be realized by the NAND-type flash memory device because of its essentially contactless structure. In addition, the NAND array can be manufactured at low cost as compared with a NOR flash memory device. The NAND-type flash memory device is the kind of data storage memory device used in USB storage devices, MP3 players, and so on. In contrast, since the NOR flash memory device has a competitive speed for data accessing and is commonly used in “Code Flash”, it is adopted in the application of cellular phone terminals.
The NOR flash memory device includes a bitline bias circuit. The bitline bias circuit performs a function to stably supply a predetermined voltage (e.g., about 1 V) to a drain of a memory cell during a read operation. A bias voltage outputted from the bitline bias circuit is provided to a gate of a bitline bias transistor. The bitline bias transistor is connected between bitline selection transistors and a sense amplifier.
In the NOR flash memory device, a voltage higher than a power voltage is applied to a gate of the bitline selection transistors. Accordingly, the bitline selection transistors are constituted by high voltage NMOS transistors having durability with respect to a high voltage. The high voltage NMOS transistors are connected serially. Also, a constant voltage below a power voltage supplied from the bitline bias circuit is applied to a gate of the bitline bias transistor. Thus, the bitline bias transistor is constituted by a conventional low voltage NMOS transistor.
The bitline bias circuit may supply a voltage close to a power voltage to the bitline bias transistor. However, it is difficult to stably supply a voltage close to the power voltage to the bitline bias transistor due to characteristics of transistors. Also, in the event that a power voltage applied to the bitline bias circuit is decreased, there is a problem that a bias voltage applied to the bitline bias transistor is also decreased.
Additionally, a conventional bitline bias circuit always should provide a bias voltage having a constant level. Since a conventional bitline bias circuit is always operated, there is a problem of large power consumption due to leakage current.